EAPI=8

DESCRIPTION="framework for Verilog RTL synthesis"
HOMEPAGE="http://www.clifford.at/yosys/"

if [ "${PV}" == "9999" ]; then
	inherit git-r3
	EGIT_REPO_URI="https://github.com/YosysHQ/${PN}"
else
	KEYWORDS="amd64"
	SRC_URI="https://github.com/YosysHQ/${PN}/archive/refs/tags/v${PV}.tar.gz -> ${P}.tar.gz"
fi

LICENSE="ISC"
SLOT=0
#PATCHES=( $FILESDIR/$PN-makefile.patch )

DEPEND="dev-vcs/git
	media-gfx/xdot
	dev-libs/boost
	llvm-core/clang"

src_compile() 
{
  emake DESTDIR="$D" PREFIX=/usr
}

src_install() 
{
  emake DESTDIR="$D" PREFIX=/usr install	
}